This invention relates to a solid state imaging device using, as pixel constituting elements, image sensors such as Charge Modulation Devices (hereinafter abbreviated as CMDs) in each of which a source-drain current is modulated depending on an amount of electric charges produced under light irradiation and integrated below a gate electrode.
While there have been conventionally known a variety of solid state imaging devices comprised of image sensors having MIS-type light receiving and integrating portions, one of those solid state imaging devices employs image sensors having MIS-type light receiving and integrating portions and also an internal amplifying function. One example of such a solid state imaging device using CMD image sensors has been proposed by the applicant of this application, and is disclosed in Japanese Patent Laid-Open No. 60-206063 and a paper entitled "A New MOS Image Sensor Operating in a Non-Destructive Readout Mode", pp. 353-356, Proceedings of International Electron Device Meeting (IEDM), 1986.
One example of arrangement of such a conventional solid state imaging device using CMD image sensors will be explained below with reference to a circuit diagram of FIG. 1. First, CMDs 101-11, 101-12, . . . , 101-mn constituting respective pixels are arranged in the form of a matrix, and a video bias V.sub.DD (&gt;0) is commonly applied to respective drains of the CMDs. Respective gate terminals of a group of CMDs in each row arrayed in the X-direction are commonly connected to corresponding one of row lines 102-1, 102-2, . . . , 102-m, whereas respective source terminals of a group of CMDs in each column arrayed in the Y-direction are commonly connected to corresponding one of column lines 103-1, 103-2, . . . , 103-n. The column lines 103-1, 103-2, . . . , 103-n are commonly connected to a signal line 106 through column select transistors 104-1, 104-2, . . . , 104-n, respectively, and also commonly connected to a reference line 107, in turn connected to GND (grounded), through non-select transistors 105-1, 105-2, . . . , 105-n, respectively. The signal line 106 is connected to a current-voltage conversion type preamplifier 112 with its input terminal virtually grounded, so that a video signal of negative polarity is time-serially read out at an output terminal 109 of the preamplifier 112.
Meanwhile, the row lines 102-1, 102-2, . . . , 102-m are connected to a vertical scanning circuit 110 and applied with signals .PHI..sub.G1, .PHI..sub.G2, . . . , .PHI..sub.Gm, respectively. Gate terminals of the column select transistors 104-1, 104-2, . . . , 104-n are directly connected to a horizontal scanning circuit 111 and applied with signals .PHI..sub.S1, .PHI..sub.S2, . . . , .PHI..sub.Sm, respectively. Gate terminals of the non-select transistors 105-1, 105-2, . . . , 105-n are connected to the horizontal scanning circuit 111 through inverters and applied with inverted ones of the signals .PHI..sub.S1, .PHI..sub.S2, . . . , .PHI..sub.Sm, respectively. The CMDs constituting the respective pixels are formed on the same substrate which is applied with substrate voltage V.sub.SUB.
FIG. 2 is a chart of signal waveforms for explaining operation of the solid state imaging device using CMD image sensors shown in FIG. 1. The signals .PHI..sub.G1, .PHI..sub.G2, . . . , .PHI..sub.Gm applied to the row lines 102-1, 102-2, . . . , 102-m each comprise readout gate voltage V.sub.RD, reset voltage V.sub.RST, overflow voltage V.sub.OF and integrating voltage V.sub.INT. Then, each non-selected row is applied with the integrating voltage V.sub.INT for a horizontal effective period of the video signal and the overflow voltage V.sub.OF for a horizontal blanking period, whereas each selected row is applied with the readout gate voltage V.sub.RD for the horizontal effective period of the video signal and the reset voltage V.sub.RST for the horizontal blanking period.
The signals .PHI..sub.S1, .PHI..sub.S2, . . . , .PHI..sub.Sn applied to the gate terminals of the column select transistors 104-1, 104-2, . . . , 104-n are signals for selecting the column lines 103-1, 103-2, . . . , 103-n, of which voltage values are set in such a manner as to turn off the column select transistors 104-1, 104-2, . . . , 104-n and on the non-select transistors 105-1, 105-2, . . . , 105-n at a low level and turn on the column select transistors 104-1, 104-2, . . . , 104-n and off the non-select transistors 105-1, 105-2, . . . , 105-n at a high level. Signals produced under light irradiation from the respective CMD pixels are sequentially read out to the signal line 106 and amplified by the preamplifier 112 for delivery to the exterior. Note that denoted by H-BLANK in FIG. 2 is a signal indicating the timing of horizontal blanking period of the video signal.
The conventional solid state imaging device as stated above has however suffered from the following disadvantage because it is designed to reset the pixels connected to the selected rows during the horizontal blanking period. Specifically, while the reset operation to determine the start points of integrating time of the pixels is line-sequentially performed row by row during the horizontal blanking period, the readout operation corresponding to the end points of integrating time is point-sequentially performed for the pixels connected to each row line. This leads to a problem that the periods of integrating time are different depending on respective positions of the pixels arrayed in the form of a matrix on the solid state imaging device.